`timescale 1ns/1ps
module tb();
	parameter CheckSeq = 6'b110010;

	bit clk ;
	bit rst_n ;
	logic Seq_in ;
	logic Done ;

	initial begin
		clk <= 0 ;
		rst_n <= 0 ;
		Seq_in <= 0 ;
		#10 ;
		rst_n <= 1 ;
		#12 ;
		#4 ;
		
		Seq_in <= 1 ;
		#4 ;
		@(posedge clk);
		Seq_in <= 1 ;
		#4 ;
		@(posedge clk);
		Seq_in <= 0 ;
		#4 ;
		@(posedge clk);
		Seq_in <= 0 ;
		#4 ;
		@(posedge clk);
		Seq_in <= 1 ;
		#4 ;
		@(posedge clk);
		Seq_in <= 0 ;
		#4 ;
		@(posedge clk);
		Seq_in <= 1 ;
		#4 ;
		@(posedge clk);
		Seq_in <= 1 ;
		#4 ;
		@(posedge clk);
		Seq_in <= 1 ;
		#4 ;
		@(posedge clk);
		Seq_in <= 1 ;
		#4 ;
		@(posedge clk);
		Seq_in <= 1 ;
		#4 ;
		@(posedge clk);
		Seq_in <= 1 ;
		#4 ;
		@(posedge clk);
		Seq_in <= 1 ;
		#100;
		$finish; 
	end

	always #2 clk = ~clk ;
	top #(
			.CheckSeqLEN(6)
		) inst_top (
			.clk    (clk),
			.rst_n  (rst_n),
			.Seq_in (Seq_in),
			.Done   (Done)
		);

	always @( * ) begin
		if(Done)
			$display("Check success!!!time at \t",$time);
	end
	
	initial begin
		$dumpfile("wave.vcd" );
		$dumpvars(0, tb ) ;

	end
endmodule:tb